134 lines
4.6 KiB
C
134 lines
4.6 KiB
C
/*
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Copyright (c) 2005-2017 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_machine_macos_common_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_machine_macos_common_H
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#include <sched.h>
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#define __TBB_Yield() sched_yield()
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// __TBB_HardwareConcurrency
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#include <sys/types.h>
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#include <sys/sysctl.h>
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static inline int __TBB_macos_available_cpu() {
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int name[2] = {CTL_HW, HW_AVAILCPU};
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int ncpu;
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size_t size = sizeof(ncpu);
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sysctl( name, 2, &ncpu, &size, NULL, 0 );
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return ncpu;
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}
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#define __TBB_HardwareConcurrency() __TBB_macos_available_cpu()
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#ifndef __TBB_full_memory_fence
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// TBB has not recognized the architecture (none of the architecture abstraction
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// headers was included).
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#define __TBB_UnknownArchitecture 1
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#endif
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#if __TBB_UnknownArchitecture
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// Implementation of atomic operations based on OS provided primitives
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#include <libkern/OSAtomic.h>
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static inline int64_t __TBB_machine_cmpswp8_OsX(volatile void *ptr, int64_t value, int64_t comparand)
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{
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__TBB_ASSERT( tbb::internal::is_aligned(ptr,8), "address not properly aligned for macOS* atomics");
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int64_t* address = (int64_t*)ptr;
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while( !OSAtomicCompareAndSwap64Barrier(comparand, value, address) ){
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#if __TBB_WORDSIZE==8
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int64_t snapshot = *address;
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#else
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int64_t snapshot = OSAtomicAdd64( 0, address );
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#endif
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if( snapshot!=comparand ) return snapshot;
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}
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return comparand;
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}
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#define __TBB_machine_cmpswp8 __TBB_machine_cmpswp8_OsX
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#endif /* __TBB_UnknownArchitecture */
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#if __TBB_UnknownArchitecture
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#ifndef __TBB_WORDSIZE
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#define __TBB_WORDSIZE __SIZEOF_POINTER__
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#endif
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#ifdef __TBB_ENDIANNESS
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// Already determined based on hardware architecture.
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#elif __BIG_ENDIAN__
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#define __TBB_ENDIANNESS __TBB_ENDIAN_BIG
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#elif __LITTLE_ENDIAN__
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#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
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#else
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#define __TBB_ENDIANNESS __TBB_ENDIAN_UNSUPPORTED
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#endif
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/** As this generic implementation has absolutely no information about underlying
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hardware, its performance most likely will be sub-optimal because of full memory
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fence usages where a more lightweight synchronization means (or none at all)
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could suffice. Thus if you use this header to enable TBB on a new platform,
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consider forking it and relaxing below helpers as appropriate. **/
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#define __TBB_control_consistency_helper() OSMemoryBarrier()
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#define __TBB_acquire_consistency_helper() OSMemoryBarrier()
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#define __TBB_release_consistency_helper() OSMemoryBarrier()
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#define __TBB_full_memory_fence() OSMemoryBarrier()
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static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand)
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{
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__TBB_ASSERT( tbb::internal::is_aligned(ptr,4), "address not properly aligned for macOS atomics");
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int32_t* address = (int32_t*)ptr;
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while( !OSAtomicCompareAndSwap32Barrier(comparand, value, address) ){
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int32_t snapshot = *address;
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if( snapshot!=comparand ) return snapshot;
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}
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return comparand;
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}
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static inline int32_t __TBB_machine_fetchadd4(volatile void *ptr, int32_t addend)
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{
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__TBB_ASSERT( tbb::internal::is_aligned(ptr,4), "address not properly aligned for macOS atomics");
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return OSAtomicAdd32Barrier(addend, (int32_t*)ptr) - addend;
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}
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static inline int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend)
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{
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__TBB_ASSERT( tbb::internal::is_aligned(ptr,8), "address not properly aligned for macOS atomics");
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return OSAtomicAdd64Barrier(addend, (int64_t*)ptr) - addend;
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}
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#define __TBB_USE_GENERIC_PART_WORD_CAS 1
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#define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
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#define __TBB_USE_GENERIC_FETCH_STORE 1
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#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
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#if __TBB_WORDSIZE == 4
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#define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1
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#endif
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#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
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#endif /* __TBB_UnknownArchitecture */
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