97 lines
4.9 KiB
C
97 lines
4.9 KiB
C
/*
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Copyright (c) 2005-2017 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_machine_linux_intel64_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_machine_linux_intel64_H
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#include <stdint.h>
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#include "gcc_ia32_common.h"
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#define __TBB_WORDSIZE 8
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#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
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#define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
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#define __TBB_control_consistency_helper() __TBB_compiler_fence()
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#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
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#define __TBB_release_consistency_helper() __TBB_compiler_fence()
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#ifndef __TBB_full_memory_fence
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#define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
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#endif
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#define __TBB_MACHINE_DEFINE_ATOMICS(S,T,X) \
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static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \
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{ \
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T result; \
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\
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__asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \
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: "=a"(result), "=m"(*(volatile T*)ptr) \
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: "q"(value), "0"(comparand), "m"(*(volatile T*)ptr) \
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: "memory"); \
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return result; \
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} \
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\
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static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \
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{ \
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T result; \
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__asm__ __volatile__("lock\nxadd" X " %0,%1" \
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: "=r"(result),"=m"(*(volatile T*)ptr) \
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: "0"(addend), "m"(*(volatile T*)ptr) \
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: "memory"); \
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return result; \
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} \
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\
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static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \
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{ \
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T result; \
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__asm__ __volatile__("lock\nxchg" X " %0,%1" \
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: "=r"(result),"=m"(*(volatile T*)ptr) \
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: "0"(value), "m"(*(volatile T*)ptr) \
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: "memory"); \
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return result; \
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} \
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__TBB_MACHINE_DEFINE_ATOMICS(1,int8_t,"")
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__TBB_MACHINE_DEFINE_ATOMICS(2,int16_t,"")
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__TBB_MACHINE_DEFINE_ATOMICS(4,int32_t,"")
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__TBB_MACHINE_DEFINE_ATOMICS(8,int64_t,"q")
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#undef __TBB_MACHINE_DEFINE_ATOMICS
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static inline void __TBB_machine_or( volatile void *ptr, uint64_t value ) {
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__asm__ __volatile__("lock\norq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(value), "m"(*(volatile uint64_t*)ptr) : "memory");
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}
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static inline void __TBB_machine_and( volatile void *ptr, uint64_t value ) {
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__asm__ __volatile__("lock\nandq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(value), "m"(*(volatile uint64_t*)ptr) : "memory");
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}
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#define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
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#define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
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#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
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#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
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