124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/*
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Copyright (c) 2005-2017 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_machine_gcc_itsx_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_machine_gcc_itsx_H
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#define __TBB_OP_XACQUIRE 0xF2
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#define __TBB_OP_XRELEASE 0xF3
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#define __TBB_OP_LOCK 0xF0
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#define __TBB_STRINGIZE_INTERNAL(arg) #arg
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#define __TBB_STRINGIZE(arg) __TBB_STRINGIZE_INTERNAL(arg)
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#ifdef __TBB_x86_64
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#define __TBB_r_out "=r"
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#else
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#define __TBB_r_out "=q"
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#endif
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inline static uint8_t __TBB_machine_try_lock_elided( volatile uint8_t* lk )
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{
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uint8_t value = 1;
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__asm__ volatile (".byte " __TBB_STRINGIZE(__TBB_OP_XACQUIRE)"; lock; xchgb %0, %1;"
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: __TBB_r_out(value), "=m"(*lk) : "0"(value), "m"(*lk) : "memory" );
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return uint8_t(value^1);
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}
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inline static void __TBB_machine_try_lock_elided_cancel()
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{
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// 'pause' instruction aborts HLE/RTM transactions
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__asm__ volatile ("pause\n" : : : "memory" );
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}
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inline static void __TBB_machine_unlock_elided( volatile uint8_t* lk )
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{
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__asm__ volatile (".byte " __TBB_STRINGIZE(__TBB_OP_XRELEASE)"; movb $0, %0"
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: "=m"(*lk) : "m"(*lk) : "memory" );
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}
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#if __TBB_TSX_INTRINSICS_PRESENT
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#include <immintrin.h>
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#define __TBB_machine_is_in_transaction _xtest
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#define __TBB_machine_begin_transaction _xbegin
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#define __TBB_machine_end_transaction _xend
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#define __TBB_machine_transaction_conflict_abort() _xabort(0xff)
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#else
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/*!
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* Check if the instruction is executed in a transaction or not
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*/
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inline static bool __TBB_machine_is_in_transaction()
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{
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int8_t res = 0;
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#if __TBB_x86_32
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__asm__ volatile (".byte 0x0F; .byte 0x01; .byte 0xD6;\n"
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"setz %0" : "=q"(res) : : "memory" );
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#else
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__asm__ volatile (".byte 0x0F; .byte 0x01; .byte 0xD6;\n"
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"setz %0" : "=r"(res) : : "memory" );
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#endif
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return res==0;
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}
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/*!
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* Enter speculative execution mode.
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* @return -1 on success
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* abort cause ( or 0 ) on abort
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*/
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inline static uint32_t __TBB_machine_begin_transaction()
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{
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uint32_t res = ~uint32_t(0); // success value
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__asm__ volatile ("1: .byte 0xC7; .byte 0xF8;\n" // XBEGIN <abort-offset>
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" .long 2f-1b-6\n" // 2f-1b == difference in addresses of start
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// of XBEGIN and the MOVL
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// 2f - 1b - 6 == that difference minus the size of the
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// XBEGIN instruction. This is the abort offset to
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// 2: below.
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" jmp 3f\n" // success (leave -1 in res)
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"2: movl %%eax,%0\n" // store failure code in res
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"3:"
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:"=r"(res):"0"(res):"memory","%eax");
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return res;
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}
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/*!
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* Attempt to commit/end transaction
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*/
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inline static void __TBB_machine_end_transaction()
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{
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__asm__ volatile (".byte 0x0F; .byte 0x01; .byte 0xD5" :::"memory"); // XEND
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}
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/*
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* aborts with code 0xFF (lock already held)
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*/
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inline static void __TBB_machine_transaction_conflict_abort()
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{
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__asm__ volatile (".byte 0xC6; .byte 0xF8; .byte 0xFF" :::"memory");
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}
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#endif /* __TBB_TSX_INTRINSICS_PRESENT */
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