172 lines
6.6 KiB
C
172 lines
6.6 KiB
C
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/*
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Copyright 2005-2016 Intel Corporation. All Rights Reserved.
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This file is part of Threading Building Blocks. Threading Building Blocks is free software;
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you can redistribute it and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation. Threading Building Blocks is
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distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details. You should have received a copy of
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the GNU General Public License along with Threading Building Blocks; if not, write to the
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Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software library without
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restriction. Specifically, if other files instantiate templates or use macros or inline
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functions from this file, or you compile this file and link it with other files to produce
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an executable, this file does not by itself cause the resulting executable to be covered
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by the GNU General Public License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General Public License.
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*/
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#if !defined(__TBB_machine_H) || defined(__TBB_msvc_armv7_H)
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#error Do not #include this internal file directly; use public TBB headers instead.
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#endif
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#define __TBB_msvc_armv7_H
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#include <intrin.h>
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#include <float.h>
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#define __TBB_WORDSIZE 4
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#define __TBB_ENDIANNESS __TBB_ENDIAN_UNSUPPORTED
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#if defined(TBB_WIN32_USE_CL_BUILTINS)
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// We can test this on _M_IX86
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#pragma intrinsic(_ReadWriteBarrier)
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#pragma intrinsic(_mm_mfence)
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#define __TBB_compiler_fence() _ReadWriteBarrier()
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#define __TBB_full_memory_fence() _mm_mfence()
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#define __TBB_control_consistency_helper() __TBB_compiler_fence()
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#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
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#define __TBB_release_consistency_helper() __TBB_compiler_fence()
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#else
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//Now __dmb(_ARM_BARRIER_SY) is used for both compiler and memory fences
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//This might be changed later after testing
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#define __TBB_compiler_fence() __dmb(_ARM_BARRIER_SY)
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#define __TBB_full_memory_fence() __dmb(_ARM_BARRIER_SY)
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#define __TBB_control_consistency_helper() __TBB_compiler_fence()
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#define __TBB_acquire_consistency_helper() __TBB_full_memory_fence()
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#define __TBB_release_consistency_helper() __TBB_full_memory_fence()
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#endif
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//--------------------------------------------------
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// Compare and swap
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//--------------------------------------------------
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/**
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* Atomic CAS for 32 bit values, if *ptr==comparand, then *ptr=value, returns *ptr
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* @param ptr pointer to value in memory to be swapped with value if *ptr==comparand
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* @param value value to assign *ptr to if *ptr==comparand
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* @param comparand value to compare with *ptr
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* @return value originally in memory at ptr, regardless of success
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*/
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#define __TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(S,T,F) \
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inline T __TBB_machine_cmpswp##S( volatile void *ptr, T value, T comparand ) { \
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return _InterlockedCompareExchange##F(reinterpret_cast<volatile T *>(ptr),value,comparand); \
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} \
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#define __TBB_MACHINE_DEFINE_ATOMICS_FETCHADD(S,T,F) \
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inline T __TBB_machine_fetchadd##S( volatile void *ptr, T value ) { \
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return _InterlockedExchangeAdd##F(reinterpret_cast<volatile T *>(ptr),value); \
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} \
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__TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(1,char,8)
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__TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(2,short,16)
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__TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(4,long,)
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__TBB_MACHINE_DEFINE_ATOMICS_CMPSWP(8,__int64,64)
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__TBB_MACHINE_DEFINE_ATOMICS_FETCHADD(4,long,)
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#if defined(TBB_WIN32_USE_CL_BUILTINS)
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// No _InterlockedExchangeAdd64 intrinsic on _M_IX86
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#define __TBB_64BIT_ATOMICS 0
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#else
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__TBB_MACHINE_DEFINE_ATOMICS_FETCHADD(8,__int64,64)
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#endif
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inline void __TBB_machine_pause (int32_t delay )
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{
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while(delay>0)
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{
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__TBB_compiler_fence();
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delay--;
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}
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}
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// API to retrieve/update FPU control setting
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#define __TBB_CPU_CTL_ENV_PRESENT 1
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namespace tbb {
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namespace internal {
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template <typename T, size_t S>
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struct machine_load_store_relaxed {
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static inline T load ( const volatile T& location ) {
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const T value = location;
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/*
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* An extra memory barrier is required for errata #761319
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* Please see http://infocenter.arm.com/help/topic/com.arm.doc.uan0004a
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*/
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__TBB_acquire_consistency_helper();
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return value;
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}
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static inline void store ( volatile T& location, T value ) {
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location = value;
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}
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};
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class cpu_ctl_env {
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private:
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unsigned int my_ctl;
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public:
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bool operator!=( const cpu_ctl_env& ctl ) const { return my_ctl != ctl.my_ctl; }
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void get_env() { my_ctl = _control87(0, 0); }
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void set_env() const { _control87( my_ctl, ~0U ); }
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};
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} // namespace internal
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} // namespaces tbb
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// Machine specific atomic operations
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#define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C)
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#define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C)
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#define __TBB_Pause(V) __TBB_machine_pause(V)
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// Use generics for some things
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#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
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#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
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#define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
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#define __TBB_USE_GENERIC_PART_WORD_FETCH_STORE 1
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#define __TBB_USE_GENERIC_FETCH_STORE 1
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#define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1
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#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
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#if defined(TBB_WIN32_USE_CL_BUILTINS)
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#if !__TBB_WIN8UI_SUPPORT
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extern "C" __declspec(dllimport) int __stdcall SwitchToThread( void );
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#define __TBB_Yield() SwitchToThread()
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#else
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#include<thread>
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#define __TBB_Yield() std::this_thread::yield()
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#endif
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#else
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#define __TBB_Yield() __yield()
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#endif
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// Machine specific atomic operations
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#define __TBB_AtomicOR(P,V) __TBB_machine_OR(P,V)
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#define __TBB_AtomicAND(P,V) __TBB_machine_AND(P,V)
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template <typename T1,typename T2>
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inline void __TBB_machine_OR( T1 *operand, T2 addend ) {
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_InterlockedOr((long volatile *)operand, (long)addend);
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}
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template <typename T1,typename T2>
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inline void __TBB_machine_AND( T1 *operand, T2 addend ) {
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_InterlockedAnd((long volatile *)operand, (long)addend);
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}
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